Design, Test and Interface of Cmos and Bicmos Opto-electronic Transceivers

Analog and mixed signal design has always been very interesting and when it comes to the design of high-speed CMOS and SiGe BiCMOS optical transceivers it becomes even more challenging. Special care has to be taken while doing the layout of such a circuit that operates at a frequency of 1 Gbps or higher. The focus of our first work was to layout an optical driver and receiver stage capable of high integration and driving VCSEL arrays that emit laser at a wavelength of 850 nm. Emphasis was given on analog CMOS design techniques because an increasing portion of today’s integrated circuit functionality is being performed in the digital domain by VLSI circuits implemented in a CMOS technology. Achieving high integration requires both the analog signal processing and the associated analog-to-digital interface to be built with the same technology as the digital circuits. The work was extended to provide a test-bench to the CFDRC-Micromesh tool that provides the capability of doing 3D electro-magnetic analysis of both analog circuits and interconnects. As the tool is capable of reading layout in the Cadence Virtuoso format, these big transceiver designs were first made Cadence compatible and then interfaced with the Micromesh tool using Cadence Skill procedures. During the process of interfacing the main idea was to preserve the terminal information that will provide Micromesh with the right interfaces for the signal flow. The second part of our work dealt with the testing and measurement of the test circuits that were designed so far. It included testing both flavors, bare die and packaged IC. This work will provide a first hand information on the proper functionality of the design done earlier. The theoretical and the practical results came under direct comparison